1. Field of the Invention
Example embodiments of the present invention may generally relate to a semiconductor chip stack structure and method thereof, and more particularly, to a chip stack package and a method for manufacturing the chip stack package.
2. Description of the Related Art
A chip stack package may include a plurality of semiconductor chips that may be mounted on a package substrate. Electrical connections may be provided to electrically connect the semiconductor chips to the package substrate. A space may be provided between an upper chip and a lower chip to accommodate the electrical connections between the lower chip and the substrate. An adhesive layer may be interposed between the upper chip and the lower chip.
For example, as shown in FIG. 1, a chip stack package may include a package substrate 110, a first chip 121 that may have bonding pads 123, a second chip 122 that may have a back surface 122b, bonding wires 140, and an adhesive layer 130 that may be interposed between the first chip 121 and the second chip 122.
A liquid adhesive may be applied to the first chip 121. The second chip 122 may be stacked on the first chip 121. Upon stacking, heat and pressure may be applied to the first chip 121, which may reduce the distance between the first chip 121 and the second chip 122 so that the bonding wires 140 of the first chip 121 may contact with the back surface 122b of the second chip 122. As a result, electrical interference may occur between the bonding wires 140 and the second chip 122, and/or bonding faults of the bonding wires 140 may occur.
As shown in FIG. 2, a chip stack package may include a package substrate 210, a first chip 221 that may have an active surface 221a, a second chip 222, bonding wires 240, and an adhesive layer 230 that may be interposed between the first chip 221 and the second chip 222. The adhesive layer 230 may have spherical spacers 250. The diameter of the spherical spacers 250 may be greater than the height (h) of the bonding wire 240 from the active surface 221a of the first chip 221.
Heat and pressure may be applied to the first chip 221 upon stacking the second chip 222 on the first chip 221. At this time, the spacers 250 may maintain the distance between the first chip 221 and the second chip 222. In this way, electrical interference that may be caused by mechanical contact between the second chip 222 and the bonding wires 240 of the first chip 221 may be reduced, and/or bonding faults of the bonding wires 240 may be reduced.
Although the conventional structures are generally thought to provide acceptable performance, they are not without shortcomings. For example, the spacers 250 may be fabricated from one of silica, polymer and/or coated metals. A protective layer may be provided on the active surface 221a of the first chip 221. The protective layer may be fabricated from an insulating resin, for example polyimide. Thermal stresses and/or mechanical shocks, which may be caused by the difference between the coefficients of thermal expansion of the spacers 250 and that of the protective layer of the first chip 221, may be applied to the active surface 221a of the first chip 221. Such stresses and/or mechanical shocks may crack the protective layer of the first chip 221 and/or damage the circuit patterns of the first chip 221.